The escalating requirements for high density and performance associated with ultra-large scale integration require responsive changes in electrical interconnect patterns, which is considered one of the most demanding aspects of ultra-large scale integration technology. Demands for ultra-large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.18 micron and under, e.g., about 0.15 micron and under.
Semiconductor devices typically comprise a substrate and elements, such as transistors and/or memory cells, thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. The formation of interconnection layers is partly accomplished utilizing conventional photolithographic techniques to form a photoresist mask comprising a pattern and transferring the pattern to an underlying layer or composite by etching the exposed underlying regions.
In accordance with conventional practices, interconnect structures comprise electrically conductive layers such as aluminum (Al), copper (Cu) or alloys thereof. In patterning the interconnect structure, an anti-reflective coating (ARC) is typically provided between the photoresist and the conductive layer to avoid deleterious reflections from the underlying conductive layer during patterning of the photoresist. For example, the ARC can reduce the reflectivity of an Al metal layer to 25-30% from a reflectivity of about 80-90%. ARCs are chosen for their optical properties and compatibility with the underlying conductive layer. Ihowever, many of the desirable ARCs, such as titanium nitride (TiN) contain basic components, such as nitrogen, which adversely interact with the photoresist material thereon during photolithographic processing, particularly in conventional deep-ultraviolet (deep-UV) resist processing, e.g., deep-UV radiation having a wavelength of about 100 nm to about 300 nm.
A conventional interconnect structure is illustrated in FIG. 1 and comprises substrate 8 with dielectric layer 10 thereon. A conductive layer 12 is formed on dielectric layer 10 and ARC 14 is formed on conductive layer 12. A photoresist layer 16, is formed on ARC 14. In very large scale integrated circuit applications, dielectric 10 has several thousand openings which can be either vias or lateral metallization lines where the metallization pattern serves to interconnect structures on or in the semiconductor substrate. Dielectric layer 10 can comprise inorganic layers such as silicon dioxide, silicon nitride, silicon oxynitride, etc. or organic layers such as polyimide or combinations of both. Conductive layer 12 typically comprises a metal layer such as Al, Cu, or alloys thereof. ARC 14 typically comprises a nitride of silicon or a nitride of a metal such as titanium, e.g., titanium nitride (TiN).
To achieve high density line wiring, photoresist coating 16 is typically a deep UV radiation sensitive pliotoresist capable of achieving line width resolutions of about 0.15 micron. During photolithographic processing, radiation is passed through mask 18 defining a desired conductive pattern to imagewise expose photoresist coating 16. After exposure to radiation, the photoresist layer is developed to form a relief pattern therein. It has been observed, however, that a residue remains at the photoresist interface and ARC, near the developed photoresist sidewall, resulting in a parabolic appearance, 22a and 22b, at the base of the photoresist known as "footing", as shown in FIG. 2 wherein elements similar to those in FIG. 1 are denoted by similar reference numerals. In FIG. 2, reference numeral 20 denotes the pliotoresist mask. The footing problem is typical of conventional photolithographic techniques employing a photoresist coating over an ARC in forming interconnections. Footing of the photoresist during patterning results in a loss of critical dimensional control in the subsequently patterned underlying conductive layer limiting the ability to resolve small spaces between conductive lines and thus limiting wiring density.
The conventional approach to the footing problem illustrated in FIG. 2 comprises the formation of a hard mask, such as silicon oxide derived from tetraethyl orthsilicate (TEOS), on the TiN ARC layer to prevent interaction of a basic component, e.g., nitrogen, in the ARC with the deep UV photoresist mask. The metal stack, however, is quite high and presents an unfavorable aspect ratio leading to an undesirably high capacitance between the metal lines and a poor etch margin. For example, a conventional metal stack comprises a lower barrier metal layer of titanium (Ti), TiN, titanium tungsten or titanium tin at a thickness of about 250 .ANG. to about 750 .ANG.. Al or an Al alloy deposited thereon typically has a thickness of about 4,000 .ANG. to about 8,000 .ANG.. The typical TiN or Ti/TiN ARC layer has a thickness of about 750 .ANG. to about 1,150 .ANG., while the hard mask typically has a thickness of at least 300 .ANG.. Thus, the typical combined thickness of the hard mask and ARC layer is about 1,500 .ANG..
Another problem attendant upon the use of a TiN as an ARC occurs in the final or uppermost metal layer, typically referred to as the bonding pad layer. The TiN ARC typically employed for the final metal layer is very difficult to remove when etching through the overlying topside protective layer to expose the Al or Al alloy surface for forming a bonding pad opening in which a bonding pad and wiring are provided for external electrical connection. For example, the TiN ARC must be separately etched from the overlying topside protective coating, which is typically an oxide, nitride or oxynitride deposited at a thickness of about 10,000 .ANG. to about 50,000 .ANG.. The topside protective coating typically has an etch rate of about 5,000 .ANG. to about 10,000 .ANG./minute; whereas, the etch rate of the TiN ARC is less than about 1,000 .ANG./minute requiring no less than about 120 seconds for etching through the TiN ARC. This etching difficulty attendant upon the use of a TiN ARC for the final metal layer is aggravated by the need to increase the thickness of the TiN ARC as geometries are reduced in order to reduce its sensitivity to bridging caused by developer penetration of the TiN ARC during masking. The penetration of a TiN ARC by developer is a known problem. See E. G. Colgan, et seq. "Formation Mechanism Of Ring Defects During Metal RIE", Jun. 7-8, 1994, VMIC CONFERENCE 1994 ISMIC-103/94/0284, pages 284-286. The problems attendant upon the use of a TiN ARC for the final metal layer also occur with the use of a Ti or Ti/TiN ARC.
In copending U.S. application Ser. No. 09/163,601 filed on Sep. 30, 1998, it was reported that certain oxide films themselves contain nitrogen or other components which adversely interact with deep UV photoresist materials as, for example, nitrogen or nitrogen products stemming from the use of silane and nitrite oxide. The invention disclosed in copending U.S. application Ser. No. 09/163,601 comprises depositing an oxide layer on a TiN ARC by plasma enhanced chemical vapor deposition (PECVD) from an organo silicon compound, such as an alkoxysilane, e.g., TEOS, or by high density plasma (HDP) oxide deposition of a silicon oxide film. Such oxide films are free of adverse interactions with a photoresist coating thereon. In U.S. Pat. No. 5,837,576 a silicon oxide nitride etching stop layer is employed to pattern a storage node of a capacitor.
In copending U.S. patent application Ser. No. 09/371,920 filed on Aug. 11, 1999, a method is disclosed comprising the use of a SiON ARC which also serves as a hard mask. The use of SION as a combined ARC/hard mask enables a reduction in the height of the metal stack, thereby reducing capacitance between metal lines and increasing circuit speed, in addition to improving etch marginality due to the reduced aspect ratio. The disclosed embodiments include forming a thin silicon oxide layer on the SiON ARC/hard mask before depositing a deep UV photoresist layer to minimize footing.
There exists a need for methodology enabling formation of a bonding pad opening with greater efficiency, reduced interwiring capacitance and improved etch marginality. There exists a particular need for such methodology in manufacturing semiconductor devices having a design rule of about 0.18 micron and under, e.g., about 0.15 micron and under.